本书详细地阐述了一种流水线12bit，75MSamples／s的ADC试验模型。该转换器在第1级4位粗转换之后的余量放大中，以简单的开环增益级代替精确的闭环运放，比传统实现方法(相同类型的商用产品)节省功耗60％以上，同时也提高了速度。对于这种替代所产生的增益的线性与非线性误差，本书在分析与建立误差模型的基础上，提出了基于统计学的可行的后台数字校准技术。实践证明，通过复杂的数字电路的算法可估算这些误差并实时地对输出进行校准。
我国在集成ADC方面，无论是设计还是其实现离国际先进水平的差蹑都较大，而关于ADC设计方面的图书也鲜见出版。因此，本书的引进出版，对我国集成电路设计，特别是高速、高精度和低功耗ADC设计方面将具有重要意义。

List of Figures
List of Tables
Acknowledgments
Preface
1. INTRODUCTION
1. Motivation
2. Overview
3. Chapter Organization
2. PERFORMANCE TRENDS
1. Introduction
2. Digital Performance Trends
3. ADC Performance Trends
3. SCALING ANALYSIS
1. Introduction
2. Basic Device Scaling from a Digital Perspective
3. Technology Metrics for Analog Circuits
4. Scaling Impact on Matching-Limited Circuits
5. Scaling Impact on Noise-Limited Circuits
4. IMPROVING ANALOG CIRCUIT EFFICIENCY
1. Introduction
2. Analog Circuit Challenges
3. The Cost of Feedback
4. Two-Stage Feedback Amplifier vs. Open-Loop Gain Stage
5. Discussion
5. OPEN-LOOP PIPELINED ADCS
1. A Brief Review of Pipelined ADCs
2. Conventional Stage Implementation
3. Open-Loop Pipeline Stages
4. Alternative Transconductor Implementations
6. DIGITAL NONLINEARITY CORRECTION
1. Overview
2. Error Model and Digital Correction
3. Alternative Error Models
7. STATISTICS-BASED PARAMETER ESTIMATION
1. Introduction
2. Modulation Approach
3. Required Sub-ADC and Sub-DAC Redundancy
4. Parameter Estimation Based on Residue Differences
5. Statistics Based Difference Estimation
6. Complete Estimation Block
7. Simulation Example
8. Discussion
8. PROTOTYPE IMPLEMENTATION
1. ADC Architecture
2. Stage 1
3. Stage 2
4. Post-Processor
9. EXPERIMENTAL RESULTS
1. Layout and Packaging
2. Test Setup
3. Measured Results
4. Post-Processor Complexity
10. CONCLUSION
1. Summary
2. Suggestions for Future Work
Appendices
A- Open-Loop Charge Redistribution
B- Estimator Variance
C- LMS Loop Analysis
1. Time Constant
2. Output Variance
3. Maximum Gain Parameters
References
Index